Qian Lou

Qian Lou

Bio

Qian Lou is a researcher and professor at the University of Central Florida, serving as Principal Investigator on projects supported by NSF, NIH, and Amazon. His research builds AI infrastructure through the co-design of models, runtime systems, and hardware. He develops efficient model architectures, mixture-of-model routing and serving, and reliable and secure execution systems. His goal is to turn advances in model capabilities into practical services with manageable computation, memory, and deployment costs.

He received the NSF CAREER Award in 2026. His work appears in leading AI, systems, and security venues, including NeurIPS, ICML, ICLR, ISCA, ASPLOS, DAC, and IEEE S&P. Before joining UCF, he was a Senior Research Scientist at Samsung AI Center in Mountain View, where his model research contributed to patents and product translation. His work has received a Samsung Research Best Paper Award and Best Paper Finalist honors at PACT and ICCAD.

Research

How can we co-design AI models and computing infrastructure to deliver greater capabilities with lower cost, predictable performance, and reliable execution?

Driven by this question, my research aims to unlock the combined potential of specialized models and computing resources. We seek to move beyond serving each model in isolation toward infrastructure that composes models, adapts execution to changing workloads, and uses hardware effectively. Through these advances, we aim to make increasingly capable AI more affordable, scale its deployment, and support demanding applications without treating efficiency, reliability, and security as afterthoughts.

We pursue this goal through three connected directions: Efficient model architectures and algorithms, Mixture-of-model serving and runtime control, and Hardware-aware, reliable execution. We develop reusable model representations and compression methods; routing, scheduling, and simulation methods that connect model choices to runtime conditions; and compiler and hardware designs that address execution cost, resilience, and secure computation. The unifying approach is cross-layer co-design: model structure informs execution, while measurements and hardware constraints guide model and system decisions.

I. Efficient model architectures and algorithms

We reduce the computation and storage needed to provide useful model capabilities through architectural innovation, compression, and quantization. These methods provide efficient building blocks for both individual models and multi-model services.

II. Mixture-of-model serving and runtime control

We study how to select and serve multiple models as a coordinated system, rather than optimizing each model independently. Routing, reasoning budgets, memory state, and scheduling must respond to both task requirements and the state of the serving infrastructure.

III. Hardware-aware, reliable execution

We connect workload requirements to compilers, memory systems, and accelerators. The aim is to improve performance without ignoring faults, resource constraints, or the additional costs of protected computation.

Connecting the directions. Model design determines what must be computed; runtime control determines which models run, when, and with what budget; compilers and hardware determine how efficiently and reliably that computation executes. Our research aims to close this loop through measurement and co-design, turning separate optimizations into more effective AI infrastructure.

Selected Publications

* indicates students and staff under my supervision. INFRAMIND and AgentServeSim are linked above as preprints. Complete publication list.

[NeurIPS 26] Chain-of-Route: State-Aware LLM Routing for Multi-Turn Conversations
Jiaqi Xue*, Mengxin Zheng, Heng Huang, Qian Lou
Advances in Neural Information Processing Systems (NeurIPS), 2026

[NeurIPS 26] Learning Latency-Aware Orchestration for Multi-Agent Systems
Xi Shi*, Mengxin Zheng, Qian Lou
Advances in Neural Information Processing Systems (NeurIPS), 2026
[Paper (PDF)]

[NeurIPS 26] CipherFlow: Hardware-Aware Compiler Framework for Low-Latency Hybrid Secure Inference
Hedong Zhang*, Mengxin Zheng, Qian Lou
Advances in Neural Information Processing Systems (NeurIPS), 2026

[ICML 26] R2-Router: A New Paradigm for LLM Routing with Reasoning
Jiaqi Xue *, Qian Lou, Jiarong Xing, Heng Huang
International Conference on Machine Learning (ICML), 2026
[Paper (PDF)]

[ISCA 26] HBM-CASO: A Coordinated Approach to HBM System-Level and On-Die ECC
Ruizhi Zhu, Yanan Guo, Huize Li, Weidong Cao, Qian Lou, Xin Xin
ACM Annual International Symposium on Computer Architecture (ISCA), 2026

[DAC 26] HW-Router: Hardware-Aware Routing for Scalable Multi-LLM Serving
Ahasan Kabir*, Jiaqi Xue, Mengxin Zheng, Qian Lou
Design Automation Conference (DAC), 2026

[ASPLOS 26] ReliaFHE: Resilient Design for Fully Homomorphic Encryption Accelerators
Fan Li, Mayank Kumar*, Ruizhi Zhu, Mengxin Zheng, Qian Lou, Xin Xin
ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2026
[Publisher]

[CVPR 22] Lite-MDETR: A Lightweight Multi-Modal Detector
Qian Lou, Yen-Chang Hsu, Burak Uzkent, Ting Hua, Yilin Shen, Hongxia Jin
IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), 2022
[Paper (PDF)]

[DAC 22] MATCHA: A Fast and Energy-Efficient Accelerator for Fully Homomorphic Encryption over the Torus
Lei Jiang, Qian Lou, Nrushad Joshi
Design Automation Conference (DAC), 2022
[Paper (PDF)]

[ICLR 22] Language model compression with weighted low-rank factorization
Yen-Chang Hsu, Ting Hua, Sungen Chang, Qian Lou, Yilin Shen, Hongxia Jin
International Conference on Learning Representations (ICLR), 2022
[Paper (PDF)]

[ICLR 22] DictFormer: Tiny Transformer with Shared Dictionary
Qian Lou, Ting Hua, Yen-Chang Hsu, Yilin Shen, Hongxia Jin
International Conference on Learning Representations (ICLR), 2022
[Paper (PDF)]

[ICLR 20] AutoQ: Automated Kernel-Wise Neural Network Quantization
Qian Lou, Feng Guo, Minje Kim, Lantao Liu, Lei Jiang
International Conference on Learning Representations (ICLR), 2020
[Paper (PDF)]

Open Source

People

Selected student contributors connect model routing, serving systems, and secure execution:

Meet the full research group.

Funding & Recognition

Support across my research program spans AI infrastructure, secure computing, healthcare AI, and education. Amazon-supported work addresses compression and post-training; NSF CAREER and CISE Core support secure computing infrastructure. Other awards support complementary applications and workforce development.

Research & Education Funding

PI: Principal Investigator. Co-PI: Co-Principal Investigator.

Honors & Recognition

All awards and recognition.

Selected Service & Outreach